A Generic VHDL Template for 2D Stencil Code Applications on FPGAs

The efficient realization of self-organizing systems based on 2D stencil code applications, like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive and also computational-intensive, because often a high number of iterations is required. FPGAs are predestined for the realization of these algorithms. They are very flexible, allow a scalable parallel processing and have a moderate power consumption, even in high-performance versions. Therefore, FPGAs are highly qualified to make these applications also real-time capable. Our goal was to implement an efficient parameterizable buffering and parallel processing scheme for such operations in FPGAs, to process them as fast as possible. We developed a generic VHDL template which allows a scalable parallelization and pipelining of 2D stencil code applications in relation to application and hardware constraints.