DocumentCode
2024089
Title
Interaction of scaling trends in processor architecture and cooling
Author
Wei Huang ; Stan, M.R. ; Gurumurthi, Sudhanva ; Ribando, Robert J ; Skadron, Kevin
Author_Institution
Dept. of Comput. Sci., Univ. of Virginia, Charlottesville, VA, USA
fYear
2010
fDate
21-25 Feb. 2010
Firstpage
198
Lastpage
204
Abstract
It is predicted that two important trends are likely to accompany traditional CMOS semiconductor technology scaling - chip multiprocessors and 3D integration. With the ever-increasing power consumption and the consequent difficulty in heat removal, it is important to consider the limits and implications of different cooling methods for the upcoming many-core and 3D era. In this paper, we consider both technology scaling and many-core architecture scaling trends in conjunction with conventional air cooling and advanced microchannel cooling for both 2D and 3D microprocessors and identify interesting inflection design points down the road.
Keywords
CMOS integrated circuits; cooling; logic design; microprocessor chips; three-dimensional integrated circuits; 2D microprocessors; 3D integration; 3D microprocessors; advanced microchannel cooling; air cooling; chip multiprocessors; cooling methods; heat removal; inflection design points; manycore architecture scaling trends; processor architecture; traditional CMOS semiconductor technology scaling; CMOS technology; Computer architecture; Computer science; Liquid cooling; Microchannel; Microprocessors; Moore´s Law; Parallel processing; Silicon; Transistors; 3D integration; Technology scaling; cooling solution; manycore architecture; processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Thermal Measurement and Management Symposium, 2010. SEMI-THERM 2010. 26th Annual IEEE
Conference_Location
Santa Clara, CA
ISSN
1065-2221
Print_ISBN
978-1-4244-9458-3
Electronic_ISBN
1065-2221
Type
conf
DOI
10.1109/STHERM.2010.5444290
Filename
5444290
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