Adaptive equalization of channel gain mismatches in ΠΔΣ ADC

Author

Kong, Shyang Kye ; Ku, Walter H.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

Volume

1

fYear

1996

fDate

18-21 Aug 1996

Firstpage

219

Abstract

The ΠΔΣ ADC architecture, proposed recently by Galton and Jensen (1995), does not require time oversampling of the input signal in principle. However, the performance of this architecture will be limited by the offset errors and channel gain mismatches due to inevitable circuits and devices mismatches. If the gains of all channels are known, the effects of channel gain mismatches may be corrected by digital post processing. The actual channel gains, however, are unknown, and we propose a simple adaptive channel gain equalization scheme to minimized the effects of the gain mismatches among channels

Keywords

adaptive equalisers; analogue-digital conversion; circuit optimisation; circuit stability; sigma-delta modulation; ΠΔΣ ADC; Hadamard sequence decomposition; adaptive equalization; channel gain mismatches; chopper stabilization; digital post processing; gain mismatch effect minimization; offset errors; Adaptive equalizers; Band pass filters; Channel bank filters; Clocks; Digital filters; Frequency conversion; Integrated circuit noise; Noise figure; Parallel architectures; Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.594098

Filename

594098