Title :
Addressable failure site test structures (AFS-TS) for process development and optimization
Author :
Doong, Kelvin Yih-Yuh ; Hsieh, Sunnys ; Lin, Sheiig-Che ; Shen, Binsan ; Chien-Jung, Wang ; Ho, Yen-Hen ; Cheng, Jye-Yen ; Yang, Yeu-Haw ; Miyamoto, Koji ; Hsu, Charles Chng-Hsiang
Author_Institution :
Worldwide Semicond. Manuf. Corp., Shinchu, Taiwan
Abstract :
Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22×6.6 mm2. By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO2 (FSG) process optimization are demonstrated.
Keywords :
failure analysis; integrated circuit testing; integrated circuit yield; logic testing; AFS-TS; SiO2:F; addressable failure site test structure; defect tracking; integrated circuit; logic backend of line process; low-k fluorinated SiO2 process; process development; process optimization; yield analysis; Circuit testing; Control systems; Expert systems; Failure analysis; Geometry; Layout; Monitoring; Semiconductor device testing; System testing; Vehicles;
Conference_Titel :
Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on
Print_ISBN :
0-7803-6275-7
DOI :
10.1109/ICMTS.2000.844404
