An electrical technique for determining MOSFET gate length reduction due to process micro-loading effects in advanced CMOS technology

Author

Liu, Chunbo ; Ma, Jamcs ; ChoI, Jeong

Author_Institution

Integrated Device Technol. Inc., Santa Clara, CA, USA

fYear

2000

fDate

2000

Firstpage

118

Lastpage

121

Abstract

A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly´s and transistors with isolated poly´s were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.

Keywords

CMOS logic circuits; MOSFET; NAND circuits; NOR circuits; Poisson equation; SPICE; integrated circuit testing; DIBL effects; I-V characteristics measurement; MOSFET gate length reduction; NAND ring oscillator circuits; NOR ring oscillator circuits; Poisson equation; advanced CMOS technology; automatic test; cross-section SEM analysis; electrical determination; four-terminal test structure; isolated poly; parallel dummy poly; process micro-loading effects; threshold voltage shift; Analytical models; CMOS process; CMOS technology; Electric resistance; Electrical resistance measurement; Isolation technology; MOSFET circuits; Testing; Transistors; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on

Print_ISBN

0-7803-6275-7

Type

conf

DOI

10.1109/ICMTS.2000.844417

Filename

844417