DocumentCode :
2026098
Title :
Influence of input voltage swing on 0.18 μm NMOS aging estimated by self-stressing testers
Author :
Chetlur, S. ; Zaneski, J. ; Mullin, L. ; Oates, A. ; Ashton, A. ; Chew, H. ; Zhou, S.
Author_Institution :
Bell Labs., Lucent Technol., Orlando, FL, USA
fYear :
2000
fDate :
2000
Firstpage :
163
Lastpage :
166
Abstract :
Self-stressing testers are used to study the impact of input voltage swing on the aging behavior of 0.18 NMOS devices in inverters. When the frequency and rise/fall time of the input pulse are altered, we demonstrate that the effective aging time ´teff´ per clock cycle varies with the rise/fall transitions and is the main factor in deciding NMOS degradation.
Keywords :
CMOS logic circuits; MOSFET; ageing; hot carriers; integrated circuit testing; 0.18 micron; NMOS aging; NMOS degradation; input voltage swing; inverters; rise/fall transitions; self-stressing testers; Accelerated aging; Automatic testing; Clocks; Frequency; Inverters; MOS devices; Oscillators; Stress; Switches; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on
Print_ISBN :
0-7803-6275-7
Type :
conf
DOI :
10.1109/ICMTS.2000.844425
Filename :
844425
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2026098
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