Design and performance evaluation of a low transistor ternary CNTFET SRAM cell

Author

Srinivasan, Pramod ; Bhat, Anirudha S. ; Murotiya, Sneh Lata ; Gupta, Anu

Author_Institution

Dept. of Electr. & Electron., Birla Inst. of Technol. & Sci., Pilani, India

fYear

2015

fDate

29-30 Jan. 2015

Firstpage

38

Lastpage

43

Abstract

Carbon Nanotube Field-Effect Transistor (CNTFET) has proved to be a promising alternative to conventional CMOS design owing to the better electrostatic control and high mobility. The paper presents a novel design of 10 Transistor ternary memory cell, with separate read and write lines. Extensive HSPICE simulations have validated the read-write functionality of the design. Besides a significant reduction in transistor count, results show at least 45% reduction in delay as compared to prevalent memory cell designs.

Keywords

SRAM chips; carbon nanotube field effect transistors; integrated circuit design; CMOS design; carbon nanotube field-effect transistor; electrostatic control; extensive HSPICE simulations; low transistor ternary CNTFET SRAM cell; performance evaluation; prevalent memory cell designs; read lines; read-write functionality; static random access memory; write lines; CNTFETs; Carbon nanotubes; Delays; Inverters; SRAM cells; CMOS; Carbon Nanotubes; Memory Cell; SRAM; Ternary Logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Computer Networks & Automated Verification (EDCAV), 2015 International Conference on

Conference_Location

Shillong

Print_ISBN

978-1-4799-6207-5

Type

conf

DOI

10.1109/EDCAV.2015.7060535

Filename

7060535