DocumentCode
2026317
Title
Optimization of low-k dielectric (fluorinated SiO2) process and evaluation of yield impact by using BEOL test structures
Author
Sunnys Hsieh ; Doong, Kelvin Yih-Yuh ; Ho, Yen-Hsuan ; Lin, Shcng-Che ; Shen, Binson ; Tseng, Sing-Mo ; Yang, Ycu-Haw ; Hsu, Charles Ching-Hsiang
Author_Institution
Worldwide Semicond. Manuf. Corp., Hsinchu, Taiwan
fYear
2000
fDate
2000
Firstpage
205
Lastpage
209
Abstract
This work describes the optimization of low-k dielectric process and evaluation of yield impact by using back end of line (BEOL) test structures. Three splits of the low-k dielectric process were compared with high-density-plasma un-doped-silicon-glass (HDP-USG) process and are electrically characterized with the test structures of the BEOL unit process and integration process parameter extraction. The interconnect capacitance is used as the optimization criteria of low-k dielectric process and the yield impact is reviewed for the concern of manufacturing.
Keywords
capacitance; dielectric thin films; integrated circuit interconnections; integrated circuit testing; integrated circuit yield; permittivity; BEOL test structures; SiO2; back end of line test structures; fluorinated SiO2 process; integration process parameter extraction; interconnect capacitance extraction; intermetal dielectric; low-k dielectric process optimisation; manufacturing; optimization criteria; yield impact; Contact resistance; Dielectric constant; Dielectric materials; Electric resistance; Manufacturing processes; Materials testing; Parameter extraction; Semiconductor device testing; System testing; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on
Print_ISBN
0-7803-6275-7
Type
conf
DOI
10.1109/ICMTS.2000.844432
Filename
844432
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