Problems encountered in various arbitration techniques used in NOC router: A survey

As technology scales down toward deep submicron, large numbers of IP blocks are being integrated on the same Silicon die, thereby enabling large amount of parallel computations, such as those required for multimedia workloads. Network-on-chip (NOC) serves as an important agent to eliminate the communication bottleneck of future multicore systems. Arbiter, a prime component has a great impact on the feasibility of router. In this paper, we concentrate our ideas on the basic arbitration techniques with their features and found some problems with their roles in improving the performance of the routers and finally extending our range to a novel notion of overcoming extensive problems of starvation, HOL, congestion, etc. in a novel and feasible manners with a combination of the existing arbitration techniques in a more compact and sequential form.