Thermal aware output polarity selection of programmable logic arrays

Intensive scaling and large number of logic blocks embedded within a VLSI chip results increased power-densities. Power-density directly converging into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area So, there is a trade-offs between area and power-density. Previous works has been done on the polarity selection of outputs of programmable logic arrays (PLA) for its reduced area or low power realization. In this paper, we present a heuristic based on genetic algorithm to increase the sharing of product terms in multi-output PLA by selecting the proper output polarity and a suitable area and power-density trade-off has been enumerated. This is the first ever effort to incorporate the power-density in polarity selection process. The proposed algorithm has been validated with the LGSynth93 benchmark circuit. A comparative study of our approach is done with `espresso´ and `espresso-Dopo´ methodology. We obtained 17.53% (26.69%) improvement in area (power-density) with respect to `espresso´. Also 7.87% in area and 27.95% in power-density with respect to `espresso-Dopo´ has been reported in this paper.