DocumentCode :
2026433
Title :
A two-week program for a platform-based SoC design
Author :
Park, Sanggyu ; Chae, Soo-Ik
Author_Institution :
Center for SoC Design Technol., Seoul Nat. Univ., South Korea
fYear :
2005
fDate :
12-14 June 2005
Firstpage :
43
Lastpage :
44
Abstract :
This paper describes a two-week program for a platform-based SoC design using SoCBase 1.0, a platform developed in the Center for SoC Design Technology. This program consists of 4 lectures and 9 laboratories. It covers several design steps from the transaction level to the FPGA prototype level for a Motion JPEG decoder. In this program we employed an SoC design flow based on SoCBase 1.0. It is targeted for graduate students and ASIC designers out in the industry. More than 100 engineers and graduate students have completed this program in 2004.
Keywords :
continuing professional development; decoding; electronic engineering education; field programmable gate arrays; image coding; system-on-chip; ASIC designers; Center for SoC Design Technology; FPGA prototype; Motion JPEG decoder; SoC design flow; SoCBase 1.0; graduate students; platform-based SoC design; transaction level; two-week program; Decoding; Design engineering; Design methodology; Electronic design automation and methodology; Field programmable gate arrays; Graphics; Job shop scheduling; Libraries; Prototypes; Virtual prototyping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Systems Education, 2005. (MSE '05). Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2374-9
Type :
conf
DOI :
10.1109/MSE.2005.15
Filename :
1509356
Link To Document :
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