Low power VLSI architecture for 2D-mesh video object motion tracking

This paper presents a low power VLSI architecture for video object motion tracking. Power has been reduced at both algorithmic and arithmetic levels. The video object is modeled as a 2D hierarchical structured mesh, where the deformation of the mesh represents the dynamics of the object across the video sequence. The algorithm benefits from the small number of bits that describe the mesh topology. Low power has been achieved in the algorithm level by: (1) modeling the mesh into independent triangular patches that can be processed in parallel, (2) each patch is hierarchical triangulated using structured technique, which can be pipelined using simple unit, and (3) using the three steps motion estimation algorithm to simplify the motion estimation of the mesh nodes. On the arithmetic level, low power has been achieved by using multiplication-free affine transformation because of the followed triangle topology. A VLSI architecture is developed based on the proposed algorithm. The architecture consists of two main parts, a mesh-based motion estimation unit and a mesh-based motion compensation unit. The first unit is based on parallel block matching motion estimation to optimize the latency. The second uses parallel threads. Each thread implements a pipelined chain of scalable multiplication-free affine units. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications such as in MPEG-4, and VRML