Teaching hardware description and verification

Since 1999, the formal methods group of the Department of Computing Science at Chalmers University of Technology has given a course on hardware description and verification (http://www.cs.chalmers.se/Cs/Education/Courses/svh/). The course focuses on the use of hardware description languages in design, and on functional verification using simulation, assertion monitoring and formal methods. The course is part of an international masters programme in dependable computer systems, although currently the majority of the students are from the 3rd and 4th years of the Chalmers undergraduate programmes in electronics or computer engineering. About 35 students pass the course each year. The emphasis in the course is on practical approaches to hardware description and verification, with students gaining hands-on experience of both commercial and academic tools. In addition, the important concepts and algorithms underlying formal verification are taught. The fact that the course manages to reflect both advanced industrial practice and state of the art research is, we feel, its major strength. The paper emphasises the benefits that the course has brought to our research group.