The ordering of events in a prototyping platform

The performance of software-based verification strategies is not keeping up with the increasing complexity of modern system-on-chip (SoC) designs. Therefore modular prototyping platforms are proposed to validate SoC designs. Most of these platforms consist of real processors combined with programmable logic, e.g. FPGA, that communicate through a board-level interconnect system. Usually, the programmable logic and the interconnect system do not run at the target clock speed of the future design. Hence, the emulated processes of the prototyping platform have to be synchronized to provide an accurate system validation. Most synchronization concepts are only able to synchronize the process data flows if data is time-independent. In this paper we present an event-based prototyping platform consisting of real processors combined with FPGAs. This platform emulates events with cycle accuracy, even though the processes operate in different scaled clock domains. Therefore we are able to validate time-dependent data flows.