Novel simple models of CML propagation delay

Author

Alioto, M. ; Palumbo, G.

Author_Institution

Dipt. Elettrico Elettronico e Sistemistico, Catania Univ., Italy

fYear

1998

fDate

19-21 Feb 1998

Firstpage

270

Lastpage

274

Abstract

Accurate and simple models of CML propagation delay are given. The approach used is new. The propagation delay is represented with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The most accurate model has a typical and worst case errors as low as 2% and 5%, respectively

Keywords

bipolar logic circuits; circuit optimisation; current-mode logic; delays; integrated circuit modelling; CML propagation delay; bipolar logic circuits; current-mode logic; electrical parameters; process parameters; worst case errors; Circuit simulation; Demultiplexing; Digital circuits; Hip; Logic circuits; Optical fiber communication; Parasitic capacitance; Propagation delay; Remotely operated vehicles; Sensitivity analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665257

Filename

665257

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2029052