Design of an asynchronous ring bus architecture for multi-core systems

In the multi-core systems, the data transfer between cores becomes a major challenge. An asynchronous ring bus, which is 33 bit width, adopting dual-rail single-track data protocol is proposed in this paper. Owning to asynchronous circuits design, there are different transfer times in different hop counts. For providing higher throughput, multiple cores which are able to access the bus simultaneously make a direct connection between each other. In bus arbitration, distribution arbiter is adopted the right to use the bus and solve the collision. Finally, the system performance in different arbitration strategies has been estimated in TSMC 0.18 μm process in this paper. The transfer time of the shortest distance is 1.5 ns approximately, and the longest distance first has a better performance in different arbitration strategies.