Title :
A Generic On-Chip Debugger for Wireless Sensor Networks
Author :
Hopkins, Andrew B T ; McDonald-Maier, Klaus D.
Author_Institution :
Dept. of Comput. Sci., Essex Univ.
Abstract :
This invited paper overviews the low level debug support hardware required for an on-chip pre-deployment debugging system for sensor networks. The solution provides significant program and data trace compression using a low complexity messaging framework. The architecture targets system-on-chip designs with multiple processor cores. The novel debug support is attached through defined interfaces making intellectual property re-use more practical. Synthesis to standard cells shows that the approach is more compact than conventional solutions. Extensions to the overviewed architecture are then proposed to allow support for both reconfigurable circuits and hybrid circuits that contain a mixture of reconfigurable and static cores
Keywords :
message passing; program debugging; program diagnostics; reconfigurable architectures; system-on-chip; telecommunication computing; wireless sensor networks; generic on-chip debugger; hybrid circuits; intellectual property reuse; low complexity messaging framework; low level debug support hardware; multiple processor cores; on-chip predeployment debugging system; program trace compression; reconfigurable circuits; system-on-chip design; wireless sensor network; Circuit synthesis; Debugging; Hardware; Intellectual property; Network synthesis; Network-on-a-chip; Process design; Sensor systems; System-on-a-chip; Wireless sensor networks;
Conference_Titel :
Adaptive Hardware and Systems, 2006. AHS 2006. First NASA/ESA Conference on
Conference_Location :
Istanbul
Print_ISBN :
0-7695-2614-4
