Power MOSFET switching waveforms: an empirical model based on a physical analysis of charge locations

This study deals with power MOSFET models. Parasitic capacitances are one of the main parameters for dynamic models, and have a critical influence on switching waveforms and switching losses. Most classical models consider that these capacitances are only mono-voltage dependent, but these models do not take into account the two (drain and gate) voltage influences on parasitic capacitances values, and consequently on switching behavior. Therefore simulation results have not been properly estimated, especially for switching losses. This aspect may appear critical for driver design or integration perspectives. Moreover, manufacturers´ datasheets offer a description of these capacitances out of nominal operation; this kind of data is not sufficient to build an accurate dynamic model of the component. In this paper, we show the inadequacy of this kind of model, by referring to a physical structure analysis of charge locations during switching transitions. Next, the article presents a new insight based on this approach. Firstly, we describe the analytical equations ruling this model with respect to critical voltage changes. After an experimental parameter extraction under nominal operation, our empirical model is established and implanted in the PSPICE simulator. Its topology allows the modeling of both voltages-depending nonlinear capacitances to be taken into account. The complete model is tested on components from various manufacturers, and results are compared with experimental curves. This model appears to be more accurate and more reliable than PSPICE or manufacturer original models. Consequently, this accuracy in switching waveforms is invaluable for driver design. It improves switching losses and EMI predictions, and could be used for optimizing the design of drive circuit (e.g. in applications such as integrated functions). This aspect appears greatly valuable for manufacturers.