Electrical characteristics of 25 mil pitch JEDEC PQFP surface mount lead frames for multichip modules

Author

Brandner, J.L.

Author_Institution

AT&T Bell Lab., Naperville, IL

fYear

1991

fDate

11-16 May 1991

Firstpage

77

Lastpage

84

Abstract

The electrical characteristics of the leadframe used to form the JEDEC standard 25-mil-pitch PQFP (POLYHIC quad flat pack) outline package are examined. The characteristic impedance is computed and three models of the leadframe pins are created for each ground configuration case for both isolated and coupled pairs of pins. Crosstalk between adjacent pins has been simulated and measured as a function of signal risetime. The risetime degradation of signals transmitted through the leadframe pins has been simulated and measured. These data have been used to estimate a conservative upper limit for clock and data rate capability of this leadframe. The POLYHIC PQFP outline package is shown to be a multi-gigabit-per-second package

Keywords

crosstalk; hybrid integrated circuits; packaging; surface mount technology; 25 mil; JEDEC standard; POLYHIC PQFP outline package; POLYHIC quad flat pack; PQFP; characteristic impedance; clock frequency limit; coupled pairs of pins; crosstalk; data rate capability; electrical characteristics; leadframe pins; multi-gigabit-per-second package; multichip modules; signal risetime; surface mount lead frames; Dielectrics; Electric variables; Frequency; Geometry; Heat sinks; Impedance; Mechanical factors; Multichip modules; Packaging; Polymer films;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1991. Proceedings., 41st

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-0012-2

Type

conf

DOI

10.1109/ECTC.1991.163857

Filename

163857