• DocumentCode
    2030185
  • Title

    Object oriented network-on-chip modeling

  • Author

    Chang, Chi-Fu ; Hsu, YarSun

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    16-18 Dec. 2010
  • Firstpage
    457
  • Lastpage
    466
  • Abstract
    The design of a NoC simulator can significantly affect its ability to explore various design space and simulation accuracy. It´s not easy to achieve both wide-range design space exploration and detailed characterization of hardware components simultaneously. This paper presents a kind of NoC modeling in an object oriented flavor: object oriented NoC modeling (“OONoC” in brief). OONoC divides the NoC design space into many design blocks and each block into many abstraction levels. OONoC can extend the exploration space of NoC, study hardware characteristics, and significantly reduce the coding effort of a new NoC design.
  • Keywords
    integrated circuit design; network-on-chip; object-oriented methods; object oriented network-on-chip modeling; wide-range design space exploration; Hardware; Object oriented modeling; Resource management; Routing; Space exploration; Switches; Unified modeling language; Design space exploration; Network-on-chip; NoC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Symposium (ICS), 2010 International
  • Conference_Location
    Tainan
  • Print_ISBN
    978-1-4244-7639-8
  • Type

    conf

  • DOI
    10.1109/COMPSYM.2010.5685466
  • Filename
    5685466