DocumentCode :
2030210
Title :
Hardware accelerated XML parsers with well form checkers and abstract classification tables
Author :
Wang, Sheng-De ; Chen, Chun-Wei ; Pan, Michael ; Hsu, Chih-Hao
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2010
fDate :
16-18 Dec. 2010
Firstpage :
467
Lastpage :
473
Abstract :
XML (Extensible Markup Language) is a general language for representation of arbitrary data structures. It has been widely used in Internet applications and in computer systems because of the extension and user customization features. In order to parse XML documents efficiently, much research has been done to accelerate the processing of XML documents or messages. The hardware-accelerated approach is becoming important due to a higher performance is getting expected. Current hardware platforms for processing XML documents lack the capability of checking the syntactic structures for XML documents because of complication. To improve existing design methods, lower the CPU load, and process XML efficiently, we present a hardware accelerated XML parser with well-form checker by using the abstract classification table. The approach provides a testing and verification platform for XML processing. Abstract classification table is an emerging indexing technique to represent the hierarchical structure of XML documents and can accelerate XML processing. In our platform, the hardware accelerator can parse XML documents at 206 Mbps and provide a Giga bit level throughput.
Keywords :
Internet; XML; abstracting; grammars; pattern classification; abstract classification; extensible markup language; hardware accelerated XML parser; well form checker; Data structures; Encoding; Hardware; Registers; Software; XML; ACT; UTF-8; VTD; XML;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Symposium (ICS), 2010 International
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-7639-8
Type :
conf
DOI :
10.1109/COMPSYM.2010.5685467
Filename :
5685467
Link To Document :
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