Formal generation of synthesizable RTL from regular programs

The complexity of the contemporary digital circuits and systems, determines the need for higher specification abstraction and automatic circuit synthesis techniques to be adopted. A prototype high level synthesis framework is presented here, that automatically generates synthesizable RTL code from unaltered, high level programs. The framework is developed using compiler-generator and logic programming (thus formal) techniques, and it utilizes a patented intermediate compilation format to retain the algorithmic semantics of the source programs and allow for compiler transformations. The synthesis framework is evaluated via statistics from a number of real-life applications. The performance optimization of the compiled applications, including an MPEG engine, underlines the quality of the prototype design framework.