DocumentCode
2030316
Title
Test generation for ultra-large circuits using ATPG constraints and test-pattern templates
Author
Wohl, Peter ; Waicukauski, John
Author_Institution
Adv. Test Technol. Inc., Williston, VT, USA
fYear
1996
fDate
20-25 Oct 1996
Firstpage
13
Lastpage
20
Abstract
When creating scan-based ATPG patterns: it is often necessary to constrain those patterns to satisfy certain conditions such as avoiding bus contention. A method is described that supports defining general pattern restrictions that are partitioned to allow efficient test generation
Keywords
automatic testing; computer testing; integrated circuit testing; logic partitioning; logic testing; ATPG constraints; contention; efficient test generation; general pattern restrictions; scan-based ATPG patterns; test generation; test-pattern templates; ultra-large circuits; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit synthesis; Circuit testing; Logic circuits; Logic testing; Microelectronics; Microprocessors; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1996. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-3541-4
Type
conf
DOI
10.1109/TEST.1996.556938
Filename
556938
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