Title :
On the diminished-1 modulo 2N+1 fused multiply-add units
Author :
Efstathiou, C. ; Voyiatzis, I.
Author_Institution :
Dept. of Inf., TEI of Athens, Athens, Greece
Abstract :
In this work the most efficient modulo 2n+1 multiplication algorithm for diminished-1 operands proposed to date is extended to compute expressions of the form |A×B + D|2n+1. The derived partial products are reduced by a carry save adder tree to two operands, which are finally added by a modulo 2n+1 adder. The proposed architecture can find applicability in systems in which fused multiply-add units can accelerate the execution of the targeting algorithms, for example digital signal processing and cryptography systems.
Keywords :
adders; carry logic; multiplying circuits; carry save adder tree; cryptography systems; digital signal processing; diminished-1 operands; fused multiply-add units; multiplication algorithm; Adders; Algorithm design and analysis; Computer architecture; Delay; Digital signal processing; Logic gates; Signal processing algorithms; DSP; RNS; Residue number system; diminished-1; modulo 2n+1; multiply-add unit;
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-61284-899-0
DOI :
10.1109/DTIS.2011.5941427
