Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Author

Pons, M. ; Barajas, E. ; Mateo, D. ; González, J.L. ; Moll, F. ; Rubio, A. ; Abella, J. ; Vera, X. ; González, A.

Author_Institution

Electron. Eng. Dept., Univ. Politec. de Catalunya, Barcelona, Spain

fYear

2011

fDate

6-8 April 2011

Firstpage

1

Lastpage

6

Abstract

Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

Keywords

CMOS integrated circuits; MOSFET; delay lock loops; field programmable gate arrays; integrated circuit layout; CMOS process; VCTA; delay; delay-locked loop design; fast time-to-market; field-programmable gate array; integrated circuits; jitter electrical simulations; size 90 nm; via-configurable transistor array regular layout fabric; Computer architecture; Delay; Jitter; Layout; Metals; Microprocessors; Transistors; Circuit Analysis; Delay Lock Loops; Design Methodology; Integrated circuit layout; Manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on

Conference_Location

Athens

Print_ISBN

978-1-61284-899-0

Type

conf

DOI

10.1109/DTIS.2011.5941428

Filename

5941428