Title :
Comparison of two leading algorithms for PLA test pattern generation
Author :
Reilova, Rafael ; Valentin, Rubi
Author_Institution :
Polytech.. Univ., Hato Rey, Puerto Rico
Abstract :
The problem of fault test generation for programmable logic arrays (PLAs) is considered. The physical device faults are viewed in terms of their effect on the logical changes of the product terms constituting the PLA. Of the four possible logical faults: growth, shrinkage, appearance and disappearance; growth fault detection and test generation are investigated. The Bose and PLAtano algorithms for generating the single-fault growth test vectors are evaluated for efficiency, generality of solution, and ease of implementation
Keywords :
automatic test software; integrated circuit testing; logic testing; programmable logic arrays; Bose algorithm; PLA test pattern generation; PLAtano algorithm; fault test generation; growth fault detection; programmable logic arrays; single-fault growth test vectors; Arc discharges; Fault detection; Input variables; Joining processes; Logic devices; Logic testing; Programmable logic arrays; Test pattern generators; Tiles;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594143
