DocumentCode :
2030721
Title :
Optimizing memory BIST Address Generator implementations
Author :
Van de Goor, Ad J. ; Kukner, Halil ; Hamdioui, Said
Author_Institution :
ComTex, Gouda, Netherlands
fYear :
2011
fDate :
6-8 April 2011
Firstpage :
1
Lastpage :
6
Abstract :
Memory Built-In Self-Test (MBIST) has become a standard industrial practice. Its quality is mainly determined by its fault detection capability in relationship to the the area overhead. The MBIST Address Generator (AG) is largely responsible for the fault detection capability, and has a significant contribution to the area overhead. This paper analyzes the properties and implementation aspects of several AGs. In addition, it presents a novel, very systematic, highspeed, low-power and low-overhead implementation, based on an Up-counter and a set of multiplexors.
Keywords :
built-in self test; memory architecture; storage allocation; built-in self-test; fault detection; memory BIST address generator; Built-in self-test; Delay; Fault detection; Generators; Logic gates; Radiation detectors; Reflective binary codes; Address Generator; Memory BIST; area; implementation aspects; power; up-only counter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-61284-899-0
Type :
conf
DOI :
10.1109/DTIS.2011.5941430
Filename :
5941430
Link To Document :
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