Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop

The zero leakage operation of Nano-electromechanical (NEM) relays has generated a lot of interest in low power logic design. Mechanical delay of the switches is orders of magnitude larger than the electrical delay and hence limits the speed of operation of NEM based digital logic circuits. The mechanical delay is inversely proportional to the gate-base voltage (V_gb). This paper presents an integrated voltage doubler based flip flop that improves the performance by 2X by overdriving V_gb. The parallel plate capacitance between the gate and base of the relay is used to realize the storage capacitor for the doubler. It has been shown that for a flop fanout of 1, 2X performance boost could be achieved with 2X increase in area and 0.5X increase in power. For larger fanouts, the doubler is shared across multiple flops minimizing the area overhead. This approach can be extended as long as the overdrive does not create any reliability issues in the device. Accurate Verilog-A models were developed based on published fabrication results of scaled NEM relays operating at 1V with a nominal air gap of 5 - 10nm. The area, power and performance trade-off for a sequential logic circuit with and without charge boosting is presented.