• DocumentCode
    2031549
  • Title

    3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design

  • Author

    Chen, Yi-Chung ; Li, Hai ; Zhang, Wei ; Pino, Robinson E.

  • Author_Institution
    Dept. of ECE, Polytech. Inst. of NYU, Brooklyn, NY, USA
  • fYear
    2011
  • fDate
    8-9 June 2011
  • Firstpage
    59
  • Lastpage
    64
  • Abstract
    Because of its simple structure, high density and good scalability, resistive random access memory (RRAM) is expected to be a promising candidate to substitute traditional data storage devices, e.g., hard-disk drive (HDD). In a conventional three-dimensional (3D) bipolar RRAM design, an isolation layer is inserted between two adjacent memory layers. The fabrication of the isolation layer introduces the extra process complexity, increases fabrication cost, and causes some potential reliability issues. In this paper, we propose a 3D High-density Interleaved Memory (3D-HIM) design for bipolar RRAM, which can eliminate the need for forming isolation layers and further improve the density of the memory island. Meanwhile, we propose a Bi-Group Operation Scheme for 3D-HIM to access multiple cells among multiple layers and to avoid unexpected overwriting. The simulation results show that the proposed design is promising for a 3D stacking RRAM application with acceptable operation margin for a 32 × 32 × 8 array in a memory island. The sensing margin degradation and programming bias confine the size of the array due to sneak path conducting currents. We diminish impact of sneak path conducting current by applying a high Ron RRAM device which can be achieved by a small-scale RRAM device.
  • Keywords
    random-access storage; 3D high-density interleaved memory; HDD; bigroup operation scheme; hard-disk drive; isolation layer; memory island; programming bias; resistive random access memory; sensing margin degradation; sneak path conducting current; three-dimensional bipolar RRAM design; traditional data storage devices; Arrays; Materials; Metals; Random access memory; Resistance; Sensors; Three dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    978-1-4577-0993-7
  • Type

    conf

  • DOI
    10.1109/NANOARCH.2011.5941484
  • Filename
    5941484