A genetic algorithm for the high-level synthesis of DSP systems for low power

This paper presents a genetic algorithm for the synthesis of VLSI low-power digital signal processing systems. The genetic algorithm operates on a high level signal flow graph of the system, which contains functional blocks such as adders, multipliers, etc. Evaluation of each design involves consideration of issues at different levels throughout the design hierarchy, such as functionality and silicon level implementation. A multi-objective genetic algorithm is used to concurrently track aspects of speed, area and power to produce optimum low power designs. A distinct feature of the genetic algorithm is the use of a library of high level transformations which is referenced by the genetic operators. The paper describes the genetic algorithm in detail and presents results showing its effectiveness with a number of signal processing systems