DocumentCode
2032085
Title
Parallel Cache Simulation on Multiprocessor Workstattions
Author
Barriga, Luis ; Ayani, Rassul
Author_Institution
Royal Institute of Technology, Sweden
Volume
1
fYear
1993
fDate
16-20 Aug. 1993
Firstpage
171
Lastpage
174
Abstract
Trace-driven simulation is the most widely used method to evaluate caches. This demands large amounts of storage and computer time. Several techniques have been proposed to reduce the simulation time of sequential trace-driven simulation. However, little has been done to exploit parallelism. In this paper, we present some efficient parallel simulation techniques that exploit set-partitioning as the main source of parallelism. We show that a straightforward implementation does not give much speedup as one might expect. We develop more efficient parallel simulation techniques by introducing more knowl edge into the cache simulator. The techniques presented here can be efficiently used on multiprocessor worksta tions.
Keywords
Cache storage; Computational modeling; Computer architecture; Computer simulation; Concurrent computing; Data structures; Delay; Parallel algorithms; Parallel processing; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 1993. ICPP 1993. International Conference on
Conference_Location
Syracuse, NY, USA
ISSN
0190-3918
Print_ISBN
0-8493-8983-6
Type
conf
DOI
10.1109/ICPP.1993.134
Filename
4134133
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