Evaluating the impact of cache interferences on numerical codes

In numerical codes, the regular interleaved accesses that occur within do-loop nests induce cache interference phe nomena that can severely degrade program performance. Cache interferences can significantly increase the volume of memory traffic and the amount of communication in uniprocessors and multiprocessors. In this paper, we iden tify cache interference phenomena, determine their causes and the conditions under which they occur. Based on these results, we derive a methodology for computing an analyt ical expression of cache misses for most classic loop nests, which can be used for precise performance analysis and prediction. We show that cache performance is unstable, because some unexpected parameters such as arrays base address can play a significant role in interference phenom ena. We also show that the impact of cache interferences can be so high, that the benefits of current data local ity optimization techniques can be partially, if not totally, eradicated.