Experimental Validation of a Performance Model for Simple Layered Task Systems

Performance modeling for the class of parallel computa tions structured as simple layered task systems is consid ered. Specifically studied are the effects of using different forms of inter-layer sequencing mechanisms. The paper refines and generalizes an earlier analytical performance model and presents the results of experimental validation of the model on two different multiprocessor systems. The experimental validation results show that the model is quite accurate, with average prediction errors in the range of only a few percent. Finally, the paper uses the model to investigate performance tradeoff issues for lay ered task systems using barrier versus explicit intertask sequencing mechanisms and implemented on computing systems with differing architectural features. This study shows that the relationship between the type of sequenc ing mechanism, the nature of the computation, and the features of the underlying architecture, interact in com plex ways to impact overall performance. Several inter esting and non-intuitive results are shown.