LFSR reseeding as a component of board level BIST

In this work we study the feasibility of LFSR reseeding as part of board and system level self test. When LFSR reseeding is included in a BIST strategy two practical aspects of this technique are crucial. These are the data volume of the encoded seeds, and the time it takes to apply LFSR reseeding as part of the self test. An existing board comprising 4 different ASICs has been used as a test case. For these ASICs we generated the required patterns and calculated the amount of storage needed for the seeds. The paper presents an estimate of the time it would take to apply LFSR reseeding to these ASICs and the impact on the total time required for ASIC level logic BIST. The paper discusses the sensitivity of the seed data volume and the reseeding application time to various parameters like the number of seeds, seed length, clock frequencies, and the number of ASICs on a board