Performance Evaluation of SIMD Processor Architectures Using Pairwise Multiplier Recoding

Research in the area of massively parallel processing with a focus on processor architecture is presented. Multiplication using conventional techniques and a modified multiplier recoding scheme for 2´s complement fixed-point multiplication is used to evaluate different SIMD architectures. Recoding is facilitated by a small amount of hardware which can be included at each processor even when the size of the individual processor is small. Performance figures are measured for 20-bit and 32-bit fixed-point multiplies, and for generation of Mandlebrot images using 20 bits and 32 bits of precision. Results indicate that although the 1 bit system has the highest cycle count for individual multiplies, this system also achieves the largest aggregate Mops rate when the systems are given equivalent processing power.