STI Gap-Fill Technology with High Aspect Ratio Process for 45nm CMOS and beyond

Author

Tilke, A.T. ; Hampp, R. ; Stapelmann, C. ; Culmsee, M. ; Conti, R. ; Wille, W. ; Jaiswal, R. ; Galiano, M. ; Jain, A.

Author_Institution

Infineon Technol., Hopewell Junction, NY

fYear

2006

fDate

22-24 May 2006

Firstpage

71

Lastpage

76

Abstract

In the present work the high aspect ratio process (HARP) using a new O₃/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gap fill in sub-65nm CMOS. We prove good gap fill performance up to aspect ratios larger 10:1. Since this fill process doesn´t attack the STI liners as compared to HDP, a variety of different STI liners can be implemented

Keywords

CMOS integrated circuits; chemical vapour deposition; isolation technology; nanotechnology; oxygen; 45 nm; CMOS integrated circuit; HARP; HDP; O₃; STI liners; TEOS; gap-fill technology; high aspect ratio process; high density plasma; nanotechnology; ozone; shallow trench isolation; sub atmospheric chemical vapor deposition; Annealing; CMOS process; CMOS technology; Chemical technology; Chemical vapor deposition; Etching; Microelectronics; Plasma applications; Plasma chemistry; Plasma devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

1-4244-0254-9

Type

conf

DOI

10.1109/ASMC.2006.1638726

Filename

1638726