DocumentCode
2032606
Title
Litho area cycle time reduction in an advanced 300mm semiconductor manufacturing line
Author
Van der Eerden, Joris ; Saenger, Tim ; Walbrick, Walter ; Niesing, Henk ; Schuurhuis, Ron
Author_Institution
ASML Netherlands BV, Veldhoven
fYear
2006
fDate
22-24 May 2006
Firstpage
114
Lastpage
119
Abstract
In this paper, we describe new methodologies used to decrease the cycle time in a semiconductor fab´s litho area. New types of analysis have been used, such as EPT for cluster systems, effective utilization, and cluster uptime
Keywords
lithography; semiconductor device manufacture; 300 mm; EPT; cluster systems; litho area cycle time reduction; semiconductor manufacturing line; Feedback loop; Fluctuations; Instruments; Lithography; Manufacturing processes; Metrology; Pulp manufacturing; Semiconductor device manufacture; USA Councils; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE
Conference_Location
Boston, MA
ISSN
1078-8743
Print_ISBN
1-4244-0254-9
Type
conf
DOI
10.1109/ASMC.2006.1638734
Filename
1638734
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