Through-Silicon Interposer (TSI) co-design optimization for high performance systems

Driven by the internet bandwidth ever increasing demand, modern logic integrated circuits (IC) need to cope for logic to memory (DRAM) data throughput above the Terabit per seconds (Tbps) range [1]. Such logic to DRAM interface is affected by the memory wall bottlenecks like: logic operating at much higher throughput and lower latency than DRAM individual modules, and with limited pin count capability organic packaging solutions leading to system architecture using serialization techniques (at the expense of power dissipation and additional circuit latency). Those bottlenecks cannot be addressed individually and need a more global approach with new packaging solutions, new devices and overall enhanced architecture. We will present in this study a silicon packaging solution that can be optimized to achieve the highest possible throughput between logic and DRAM. First, we will explain the concept of high performance silicon carrier with its key specifications as well as the metrics to be analyzed, and then we will provide design rules guidelines and a methodology to optimize such silicon carrier for the highest possible throughput performance.