DocumentCode
2032783
Title
A dynamic timing delay for accurate gate-level circuit simulation
Author
Tang, T. ; Zhou, X.
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
Volume
1
fYear
1996
fDate
18-21 Aug 1996
Firstpage
325
Abstract
A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models
Keywords
circuit analysis computing; delays; digital integrated circuits; timing; dynamic delay model; dynamic timing delay; gate-level circuit simulation; gate-level timing simulation; input transition time; multiple-input triggering; nonlinear loading effect; Capacitance; Chip scale packaging; Circuit simulation; Delay effects; Digital circuits; Digital systems; Logic circuits; Logic devices; Logic gates; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location
Ames, IA
Print_ISBN
0-7803-3636-4
Type
conf
DOI
10.1109/MWSCAS.1996.594156
Filename
594156
Link To Document