• DocumentCode
    2032801
  • Title

    The effect of TSV design parameters on the manufacturability of TSV interposers

  • Author

    Chan, Yuen Sing ; Hong Yu Li ; Xiaowu Zhang

  • Author_Institution
    Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
  • fYear
    2012
  • fDate
    5-7 Dec. 2012
  • Firstpage
    112
  • Lastpage
    118
  • Abstract
    TSV interposer is expected to be the driving vehicle for 2.5-D IC integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult for one to justify whether a TSV design or an interposer design is manufacturable or not because we are still lack of experimental reliability data. This investigation has provided this important experimental data, and also a series of correlation studies by finite element simulations. A 2-D analytical solution was also examined to help understanding the physics of the problem. Regarding the experimental results, wafer cracking was observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300 °C. The critical strength to wafer cracking was determined to be 388 MPa from some finite element analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking was found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers was ultimately generated based on the modification of the 2-D solution.
  • Keywords
    annealing; copper; finite element analysis; integrated circuit design; integrated circuit reliability; three-dimensional integrated circuits; 2.5D IC integration; 2D analytical solution; TSV arrays; TSV design parameters; TSV diameter; TSV interposer manufacturability; annealing; barrier layer thickness; copper-filled TSV interposers; dielectric layer thickness; experimental reliability data; finite element simulations; interposer design; pitch-to-diameter ratios; temperature 300 degC; thermomechanical reliability; wafer cracking; Finite element analysis; Iron; Reliability; Semiconductor device modeling; Silicon; Stress; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4673-4553-8
  • Electronic_ISBN
    978-1-4673-4551-4
  • Type

    conf

  • DOI
    10.1109/EPTC.2012.6507062
  • Filename
    6507062