An effective BIST scheme for datapaths

Datapath architectures are widely used in today´s complex integrated circuits, such as commercial microprocessors or specialized digital signal processors. A very effective BIST scheme for general datapaths is introduced in this paper. This scheme requires the register transfer (RT) level description of a datapath design, since it is independent of specific implementations of the functional modules. The novel BIST scheme is generic, i.e. independent of the datapath width. Hence, it is well suited for fixed-width datapaths that suffer from testability problems due to the truncation of the low order half part of multiplications. A simplified version of the scheme can also be applied to non fixed-width datapaths. The deterministic BIST patterns applied, always guarantee more than 99% fault coverage, for the entire datapath, within few hundreds of clock cycles. This result is achieved by exploiting the inherent operational parallelism of datapaths. The scheme imposes small area overhead and near-zero delay overhead