Title :
Approximate computing: An integrated hardware approach
Author :
Chippa, Vinay K. ; Venkataramani, Swagath ; Chakradhar, Srimat T. ; Roy, Kaushik ; Raghunathan, Anand
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Computing today is largely not about calculating a precise numerical end result. Instead, computing platforms are increasingly used to execute applications (such as search, analytics, sensor data processing, recognition, mining, and synthesis) for which “correctness” is defined as producing results that are good enough, or of sufficient quality. These applications are often intrinsically resilient to a large fraction of their computations being executed in an imprecise or approximate manner. However, the design of computing platforms continues to be guided by the principle that every computation must be executed with the same strict notion of correctness. Approximate computing departs from this long-held dogma, and exploits intrinsic application resilience to improve the efficiency (energy or speed) of computing platforms. We describe an integrated approach to approximate computing in hardware that consists of three key components. First, we present an automatic resilience characterization framework that allows the designer to quantitatively evaluate the intrinsic resilience of an application, and to quickly assess the potential of various approximate computing techniques. We then describe scalable effort hardware, an approach to approximate computing wherein hardware is designed with various scaling mechanisms, or knobs that modulate the effort expended towards correctly performing an application´s computations. Scaling mechanisms are identified at the algorithm, architecture, and circuit levels, and embodied in the hardware to provide a rich trade-off between computational accuracy and energy. Finally, dynamic effort scaling is proposed as a feedback control approach to modulate the scaling mechanisms at runtime in response to varying application requirements and data characteristics. To demonstrate the proposed concepts, we have designed and fabricated an energy-efficient Recognition and Mining (RM) processor in the TSMC 65nm process technology.- Our measurement results demonstrate that approximate computing leads to 2-20X energy savings with minimal impact on output quality across a range of applications.
Keywords :
data mining; feedback; microprocessor chips; pattern recognition; RM processor; application requirements; approximate computing; automatic resilience characterization framework; computing platforms; correctness notion; data characteristics; dynamic effort scaling; energy-efficient recognition-and-mining processor; feedback control approach; integrated hardware approach; intrinsic application resilience; scalable effort hardware; scaling mechanisms; size 65 nm; Algorithm design and analysis; Approximation methods; Computational modeling; Computer architecture; Hardware; Kernel; Resilience;
Conference_Titel :
Signals, Systems and Computers, 2013 Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4799-2388-5
DOI :
10.1109/ACSSC.2013.6810241