Title :
VSTA: A prolog-Based Formal Verifier for Systtolic Array Designs
Author :
Ling, Nam ; Shih, Timorhy
Author_Institution :
Santa Clara University, Santa Clara, CA.
Abstract :
Special purpose formal design verifier for a specific class of archirecture has the advantage of being able to exploit the dtributes of that architecture class to produce efficiency in the design verrification process.
Keywords :
Concurrent computing; Debugging; Delay; Encoding; Formal verification; Hip; Parallel processing; Process design; Systolic arrays; Topology;
Conference_Titel :
Parallel Processing, 1993. ICPP 1993. International Conference on
Conference_Location :
Syracuse, NY, USA
Print_ISBN :
0-8493-8983-6
DOI :
10.1109/ICPP.1993.185
