DocumentCode
2033425
Title
Deep Trench Top Collar Oxide Etching for DRAM Manufacturing
Author
Zheng, Guowen ; Skinner, Gary
Author_Institution
Infineon Technol., Sandston, VA
fYear
2006
fDate
22-24 May 2006
Firstpage
241
Lastpage
244
Abstract
In the fabrication of deep trenches (DT) used as the storage capacitors in DRAMs, precise formation of the lateral oxide isolation inside the trench $the "collar" - is one of the key process modules. The collar formation involves DT top oxide etching following furnace oxide growth. Careful optimization of the most critical oxide etch step is necessary. In this paper, the etch process parameters impacting the net collar oxide removal rate are discussed, followed by etch chamber conditioning optimization. Etch process endpoint challenges and solutions are also investigated
Keywords
DRAM chips; etching; integrated circuit manufacture; isolation technology; DRAM manufacturing; critical oxide etch step; deep trench top collar oxide etching; etch chamber conditioning optimization; furnace oxide growth; lateral oxide isolation; net collar oxide removal rate; storage capacitors; Capacitors; Etching; Fabrication; Furnaces; Isolation technology; Manufacturing; Plasma density; Radio frequency; Random access memory; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE
Conference_Location
Boston, MA
ISSN
1078-8743
Print_ISBN
1-4244-0254-9
Type
conf
DOI
10.1109/ASMC.2006.1638761
Filename
1638761
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