DocumentCode :
2033468
Title :
Investigation of 300 mm TSV wafer flatness with via middle scheme
Author :
Li HongYu ; Xie Jielin ; Li Weihong ; Teo Keng Hwa
Author_Institution :
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear :
2012
fDate :
5-7 Dec. 2012
Firstpage :
240
Lastpage :
243
Abstract :
Wafer flatness was monitored and investigated within TSV process development from TSV liner deposition to Cu CMP. The highest wafer bow height (455μm) was observed after TSV Cu annealing (410°C, 30mins) and second wafer bow height (-228μm) was shown after barrier metal and Cu seed sputtering. 5KÅ Ti barrier metal and 8KÅ Cu seed contributed bow height within TSV Cu annealing. To study the contribution of 5KÅ Ti and 8KÅ Cu seed, those films were separately deposited on blank wafers. 5KÅ Ti induced more wafer warpage compare with 8KÅ Cu base on the FSM measurement results. PVD Ti deposition chamber was improved and process was optimized. TSV PVD process stress on wafer bow height is reduced from -221.6μm to -58.1μm while TSV was solid filled with Cu.
Keywords :
chemical mechanical polishing; plasma CVD; three-dimensional integrated circuits; wafer bonding; Cu; Cu CMP; Cu seed sputtering; PVD Ti deposition chamber; TSV Cu annealing; TSV liner deposition; TSV process development; TSV wafer flatness; Ti barrier metal; blank wafers; middle scheme; size 300 mm; size 455 mum; temperature 410 degC; time 30 min; wafer bow height; wafer warpage; Annealing; Films; Metals; Solids; Stress; Surface treatment; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4553-8
Electronic_ISBN :
978-1-4673-4551-4
Type :
conf
DOI :
10.1109/EPTC.2012.6507085
Filename :
6507085
Link To Document :
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