Comparative study of low-leakage SRAM structures using 90nm CMOS technology

In this paper, we compared two innovations in SRAM structures, the 7T and 8T structures, over the conventional 6T structure. These two structures aim to bring down the total leakage as it becomes one of the limiting factors in submicron design. The three structures were simulated in HSPICE using the 90nm CMOS models under three varying conditions: Typical (1V, 25°C), Best (1.1V, -40°C) and Worst (0.9V, 125°C). Using the simulation results, the three were compared based on the following metrics: leakage current, static noise margin (SNM) and read and write performance. The 8T structure exhibits reduced gate tunneling current by 47.4% and 35.2%, and 83.39% and 97.73% lower in total leakage current than 6T and 7T respectively. The simulation results for SNM also shows that the structure has the greatest improvement by 1.31 times compared to 6T and 7T. For the read `0´ operation, 7T and 8T show a degradation performance by 60.8% and 18.1% and also a reduced performance during a write `1´ operation by 1.5% and 22% respectively compared to a 6T structure. But for a write `0´ operation, 7T and 8T increased their performance by 17.35% and 13.3% respectively compared to 6T.