A hybrid panel embedding process for fanout

As die sizes shrink with technology node advances, the area of WLCSP dice is becoming too small to accommodate all of the solder balls required for the dice I/O. One solution to this problem has been Fan Out Wafer Level Packages (FOWLP), which have been in volume production for over three years. However, these are Wafer processes, performed with either 200mm or 300mm reconstituted molded wafers, and are often not cost competitive with other traditional packages. A lower cost solution is needed to use for fanning out the I/O of small die that approximates the structure of the FOWLP. We have developed a panel process that uses a similar simple single Redistribution Layer (RDL) for the fan out function that complements the FOWLP solution.