ESD simulation on GGNMOS for 40V BCD

In this paper, TCAD was used to simulate GGNMOS (Grounded-Gate NMOS) as an ESD protection device for 40V BCD. The physic models and the calibration method are discussed in order to get better accuracy on the result. The effects of device parameter on the ESD robustness are investigated by device simulation in order to achieve the desired ESD design window. The simulated holding voltage is in agreement with BJT model that already proven has an agreement with silicon result. Finally, the ESD design window for 40V BCD device can be obtained by changing some device parameters.