• DocumentCode
    2033987
  • Title

    Thin glass substrates development and integration for through glass vias (TGV) with Cu interconnect

  • Author

    Bor Kai Wang ; Yi-An Chen ; Shorey, Aric ; Piech, Garrett

  • Author_Institution
    Corning Adv. Technol. Center/Corning Inc., Taipei, Taiwan
  • fYear
    2012
  • fDate
    5-7 Dec. 2012
  • Firstpage
    351
  • Lastpage
    354
  • Abstract
    Through silicon via (TSV) containing interposers have been widely discussed and applied to Three-Dimensional Stacked Integrated Circuit (3D-IC) integration. Advanced silicon interposers could be derived from three essential technologies: frontside multi-level-metallization, through-substrate-via and backside metallization. The approaches used for these technologies depend upon the application requirements, especially for the TSV technology. Process development, optimization, and cost still remain as the main issue to the industry.
  • Keywords
    circuit optimisation; copper; integrated circuit metallisation; three-dimensional integrated circuits; 3D-IC integration; Cu; Cu interconnect; TGV; TSV; backside metallization; multilevel-metallization; optimization; silicon interposers; thin glass substrates; three-dimensional stacked integrated circuit; through glass vias; through silicon via; through-substrate-via; Filling; Glass; Rough surfaces; Silicon; Substrates; Surface roughness; Surface treatment;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4673-4553-8
  • Electronic_ISBN
    978-1-4673-4551-4
  • Type

    conf

  • DOI
    10.1109/EPTC.2012.6507106
  • Filename
    6507106