Implementation of Convolutional encoder and Viterbi decoder using Verilog HDL

Author

Kavinilavu, V. ; Salivahanan, S. ; Bhaaskaran, V. S Kanchana ; Sakthikumaran, Samiappa ; Brindha, B. ; Vinoth, C.

Author_Institution

SSN Coll. of Eng., Chennai, India

Volume

1

fYear

2011

fDate

8-10 April 2011

Firstpage

297

Lastpage

300

Abstract

A Viterbi decoder uses the Viterbi algorithm for decoding a bit stream that has been encoded using Forward error correction based on a Convolutional code. The maximum likelihood detection of a digital stream is possible by Viterbi algorithm. In this paper, we present a Convolutional encoder and Viterbi decoder with a constraint length of 7 and code rate of 1/2. This is realized using Verilog HDL. It is simulated and synthesized using Modelsim PE 10.0e and Xilinx 12.4i.

Keywords

Viterbi decoding; codecs; convolutional codes; forward error correction; hardware description languages; maximum likelihood detection; Modelsim PE 10.0e; Verilog HDL; Viterbi decoder; Xilinx 12.4i; convolutional encoder; forward error correction; maximum likelihood detection; Convolutional codes; Encoding; Hardware design languages; Maximum likelihood decoding; Measurement; Viterbi algorithm; Convolutional encoder; Verilog HDL; Viterbi Algorithm; Viterbi decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Computer Technology (ICECT), 2011 3rd International Conference on

Conference_Location

Kanyakumari

Print_ISBN

978-1-4244-8678-6

Electronic_ISBN

978-1-4244-8679-3

Type

conf

DOI

10.1109/ICECTECH.2011.5941609

Filename

5941609